Dr. Peter Hofstee, distinguished research staff member at IBM will give a presentation during the CAII Seminar Series on Monday, March 1 at 11:00 a.m. The talk is titled “A Shared-memory Approach to Big Data and Analytics."
View Seminar here: https://go.ncsa.illinois.edu/CAIISpringSemesterSeriesSP21
Abstract: This talk explores how the confluence of a number of technological advances is likely to substantially change how (large) systems are organized. The first of these is to use memory more efficiently within the compute node by allowing all processing elements and adapters the same access to memory that was once reserved for processors. The second is to make technologies that offer a lower cost per bit ( but at higher latency ) available as main memory. A third is standardization of in-memory data formats, allowing memory sharing across languages, frameworks, and applications. A fourth, building on the same underlying technological trends that allow memory sharing within the node is to disaggregate memory across compute nodes and to allow nodes to steal or (non-coherently) share each other's memory. A fifth advance is architecture and language contributions that increase memory latency tolerance in microprocessors and accelerators.
We will illustrate most of these advances through technologies introduced on the IBM power architecture processors, starting with the Cell Broadband Engine in 2005 and culminating with the recently introduced POWER 10 processor.
The combination of these advances will likely lead to new, more memory-centric paradigms for computing on large datasets. We give a number of practical examples and end the talk by laying out a number of research challenges associated with these new ways of building systems.
Peter Hofstee is an IBM distinguished research staff member in the power systems performance organization in Austin, TX and a professor ( part time ) at Delft Technical University in the Netherlands. He is best known for his contributions to heterogeneous computing as the architect of the synergistic processor elements in the Cell Broadband Engine processor, used in the Sony Playstation 3 and in the Roadrunner supercomputer that was the first computer to break the Petaflop Linpack barrier. He has continued his work in heterogeneous computing by working on shared-memory compute at the node level by leading the development of an FPGA-based prototype of a shared memory interface for external processing elements on POWER 7 ( productized as CAPI on POWER 8 ). He worked with IBM research in Ireland to develop an FPGA-based prototype on POWER 9 for memory sharing between nodes, which also helped lead to a new "Memory Inception" capability on the POWER 10 processor. He draws much of his inspiration from large problems in Big Data and Analytics. Peter holds a doctorandus degree in theoretical physics from Groningen university, and a PhD in computer science from Caltech. He holds well over 100 US patents and has published widely.
All presentations will be recorded and will be available on the CAII website shortly after the presentation.