Quantum computation has potential to solve problems that are out of reach for today’s classical computers. Many of the proposed applications for quantum computers (QCs), such as those in chemistry, material science, and optimization, are capable of substantial human impact. However, the full promise of quantum will only be realized if better qubits and QCs emerge that are capable of large-scale computation. The roadmap to QC scaling does not only contain a single path but many that run in parallel. In addition to pursuing devices with more qubits, quantum researchers must 1) co-design software that pushes the frontier of existing machines and 2) build models that guide future QC design toward optimized performance. In this talk, I discuss the why, what, and how involved with scaling today’s QCs. First, I motivate the pursuit of quantum computing and introduce fundamental concepts. Next, I present a case study that explores optimized quantum circuit compilation, reducing decoherence via circuit slack. I show how quantum algorithms can adapt to the unique characteristics of today’s QCs through optimized gate scheduling, leading to significant improvements in success during runtime. In the third part of this talk, hardware challenges that restrict the number qubits on-chip are highlighted. With a focus on fixed-frequency transmon QCs, I explore the viability of modular architectures to scale quantum devices, presenting promising results in terms of yield, gate performance, and application-based analysis. Finally, an outlook is given on future directions in QC software and hardware co-design that aim to accelerate progress toward achieving practical quantum machines.
Kaitlin is a quantum software manager at Super.tech, a software division of Infleqtion. From 2020-2022, she was an IBM and Chicago Quantum Exchange Postdoctoral Scholar in the University of Chicago’s Department of Computer Science, advised by Prof. Fred Chong. Kaitlin is a co-author of the 2022 IEEE International Symposium on High-Performance Computer Architecture (HPCA) Best Paper, named a 2021 MIT EECS Rising Star, and the recipient of the 2021 IEEE Computer Society Technical Committee on Multiple Valued Logic (TC-MVL) Early Career Award in Microelectronics.
Faculty Host: Saugata Ghose
Meeting ID: 834 4978 2091 ; Password: csillinois