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MatSE Hard Materials Seminar - “Spins, bits, and flips: Essentials for high-density magnetic random-access memory”

Event Type
Materials Science and Engineering Department
100 Materials Science and Engineering Building
Mar 31, 2022   4:00 pm  
Tiffany Santos, Non-Volatile Memory Materials Research, Western Digital - San Jose
Originating Calendar
MatSE Hard Materials Seminar Calendar

“Spins, bits, and flips: Essentials for high-density magnetic random-access memory”

The magnetic tunnel junction (MTJ), a device comprised of two ferromagnetic electrodes with a thin (about 1 nm) insulating tunnel barrier in between, was first proposed in a Ph.D. thesis by Michel Jullière in 1975 and reached widespread commercialization nearly 30 years later as the read sensor in hard disk drives. MTJs became essential for data storage in consumer laptop and desktop computers, early-generation iPods, and now in data centers that store the information in “the Cloud.” The application of MTJs has expanded even further, becoming the storage element in non-volatile memory, first in toggle magnetic random access memory (MRAM) used in automotive applications and outer space, and now in the production of spin-transfer torque MRAM as a replacement for embedded flash memory. As computing capabilities advance and drive demand for high-performance memory, innovation in MTJs continues in order to deliver faster, high-density MRAM that can support last-level cache, in-memory computing, and artificial intelligence.

In this talk, I will describe the seminal discoveries that enabled MTJs for pervasive use in hard disk drives, MRAM, and magnetic sensors. As the demand for faster and higher density memory persists, still more breakthroughs are needed for MTJs contained in device pillars (or bits) just tens of nanometers in diameter. These advances require tuning of material properties at the atomic scale as well as across arrays of millions of bits in a memory chip. I will describe the magnetic properties of MTJs that are essential for high-performance MRAM and how to engineer these properties to deliver high spin-transfer torque efficiency and high data retention. In addition, I will describe the fabrication and individual addressing of MRAM bits in a 50nm full pitch array, as a step toward achieving high-density MRAM.

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