Grainger College of Engineering, All Events

Monolithic three-dimensional (3D) integration offers a promising route to overcome the limitations of conventional lateral scaling by increasing device packing density, reducing interconnect length, and improving energy efficiency and interconnect bandwidth. However, its practical implementation remains challenging because top-tier devices must be formed under a thermal budget compatible with back-end-of-line (BEOL) integration. In this talk, I will present monolithic 3D integration of silicon transistors in which ultrathin (<10 nm), uniformly doped single-crystalline silicon nanomembranes are vertically stacked on wafer scale to realize multi-tier integration of complementary p- and n-type junctionless transistors with high current density and sub-10 nm inter-tier alignment, all sequentially fabricated over the same starting wafer under a processing temperature of 400 °C or below. Based on this approach, we demonstrate vertically integrated complementary logic circuits, including inverters, NAND and NOR gates, as well as static random-access memory (SRAM) cells, with transistor‑level vertical granularity and significantly reduced circuit footprint.