Over the past decade, wireline data rates have doubled about every three-to-four years to keep pace with aggregate system bandwidth requirements. Electrical signaling standards for networking, telecom and storage applications – including Ethernet and OIF-CEI – tend to be the first to define the path to increase line rates. Today, links at 28-56Gb/s/lane are being deployed. Meanwhile, standards for 112Gb/s are being defined, and we are seeing early demonstrations of transceivers and components meeting this bandwidth. This presentation will provide an overview of standards, circuit architectures and design tradeoffs for high-speed SerDes interconnects. It will start by providing a summary of recent data rate scaling trends and standards for 28-56Gb/s and show where wireline is used in high-performance systems. Next it will describe the key tradeoffs for increasing aggregate bandwidth, including power, channel quality and process technology capability. Then it will discuss how recent standards have balanced these tradeoffs, and describe the implications for circuit architecture and design, including equalization, clocking, modulation and error correction. It will highlight some emerging trends in SerDes architecture, like ADC/DAC-based architectures, PAM-4 modulation and forward error correction. Finally we will summarize design data points from industry and academic publications for 28-112Gb/s.