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Trevor E. Carlson "The NOREBA Non-Speculative Out-of-Order Commit Processor"

Event Type
Seminar/Symposium
Sponsor
Architecture, Compilers, and Parallel Computing, Department of Computer Science, University of Illinois
Location
4124 SC; https://illinois.zoom.us/j/83325622911?pwd=RGlQUlM4TlNGSEVJTElPVkI2ZWc1dz09
Date
Dec 15, 2021   11:00 am  
Speaker
Dr. Trevor E. Carlson, Assistant Professor, National University of Singapore
Contact
Candice Steidinger
E-Mail
steidin2@illinois.edu
Phone
217-300-8564
Views
50
Originating Calendar
Computer Science Speakers Calendar

Abstract:

While many computer architecture researchers now look to accelerators as a way to improve the performance and efficiency for specific classes of workloads, the CPU remains one of the few solutions that continues to dominate the compute landscape, providing a level of flexibility and performance that is unmatched by other solutions. But, building a processor that can continue to find additional work and push the envelope in performance can to be a challenge, especially for general-purpose applications. What is needed to continue the pace of improvement is a new way to look at the applications on hand to enable fast and efficient application progress.

In this talk, I will discuss our recent work, NOREBA, a hardware-software co-designed processor that enables efficient non-speculative out-of-order commit execution. By exposing additional non-speculative work, this processor can execute, commit, and reclaim precious hardware resources to allow it to continue to make forward progress. To enable higher performance and efficiency, we inform the hardware about non-speculative work after branches by using an up-front compiler analysis pass. We also enable the processor to efficiently commit instructions out-of-order with lightweight instruction re-ordering hardware. Taken together, the resulting NOREBA core can improve performance by up to 217% (22% on average), with just a 4% increase in power.

Bio:

Trevor E. Carlson is an assistant professor at the National University of Singapore (NUS). His research interests include efficient general-purpose processing, secure systems, acceleration and simulation methodologies. His recent works include NOREBA, an efficient, out-of-order commit processor (ASPLOS 2021), Elasticlave, a high-performance TEE (USENIX Security 2022), a next generation simulation methodology, LoopPoint (HPCA 2022) and a highly parallel graph accelerator, GraphWave (DATE 2022). He co-develops the Sniper Multi-Core Simulator, which is being used by hundreds of researchers in academia and industry to evaluate the performance and power-efficiency of next generation systems. He has almost two decades of computer systems and architecture experience in both industry and academia, and his work has received six Best Paper or Best Paper Nominations in conferences such as the International Symposium on Microarchitecture (MICRO) and the International Symposium on Performance Analysis of Systems and Software (ISPASS).

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