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Joint CS/ECE Special Seminar: Marcelo Onenes Vera, "Navigating Heterogeneity and Scalability in Modern Chip Design"

Event Type
Seminar/Symposium
Sponsor
Illinois Computer Science
Location
B02 CSL and online https://illinois.zoom.us/j/84708614453?pwd=WEl6NythRUZyOWZDUGRVVm0xUzNjZz09
Virtual
wifi event
Date
Jan 31, 2024   10:00 am  
Views
60
Originating Calendar
Computer Science Special Seminar Series

Zoom: https://illinois.zoom.us/j/84708614453?pwd=WEl6NythRUZyOWZDUGRVVm0xUzNjZz09

Abstract:
The pursuit of continued improvements in performance and energy efficiency, following the end of Moore's Law and Dennard scaling, marks a pivotal moment in system architecture. As modern systems leverage parallelism and hardware specialization to achieve these goals, new challenges arise:

(1) The complexity of the system grows with the number of distinct hardware components, making it difficult to verify that it will behave correctly and securely;

(2) Parallelizing applications across more processing elements (PEs) increases the pressure on the memory hierarchy and the network to supply data to the PEs, which results in severe bottlenecks for data- and communication-intensive applications such as graph analytics and sparse linear algebra.

These challenges call for re-thinking our software abstractions and hardware designs to achieve scalable and efficient systems, as well as introducing robust methodologies to ensure their correctness and security.

This talk presents my work on scalable data-centric architectures that co-design the hardware with the migrate-compute-to-the-data programming model to outperform the best results from the Graph500 list. Moreover, this architecture offers a chiplet-based design that enables post-silicon re-configuration of critical resources like the memory hierarchy or network-on-chip for a cost-efficient integration based on different deployment targets.

In addition, this talk also introduces two formal-verification-based tools that assist the design of verifiably correct and secure hardware RTL by leveraging high-level abstraction primitives and large language models. In addition to facilitating the design process, my verification work also identified and fixed security vulnerabilities and correctness bugs in widely used open-source hardware projects.

Bio:
Marcelo is a PhD candidate at Princeton University advised by Margaret Martonosi and David Wentzlaff. He received his BSE from University of Murcia. His research focuses on Computer Architecture, from hardware RTL design and verification to software programming models of novel architectures. He has previously worked in the hardware industry at Arm, contributing to the design and verification of three GPU projects; at Cerebras Systems, creating High-Performance Computing kernels; and at AMD Research, working towards designing the next generation data centers optimized for large graph data structure traversal. At Princeton, he has contributed in two academic chip tapeouts that aims to improve the performance, power and programmability of several emerging workflows in the broad areas of Machine Learning and Graph Analytics. His contributions to scalable data-centric architectures were recognized with the gold medal at the ACM/SIGMICRO 2022 SRC and with an honorable mention at the IEEE Top Picks of 2023.

Faculty Host: 

Meeting ID: 847 0861 4453 ; Password: 362021

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