Abstract:
There have been few high-impact deployments of hardware implementations of cryptographic primitives. We present the benefits and challenges of hardware acceleration of sophisticated cryptographic primitives and protocols, and describe our past work on accelerating fully homomorphic encryption. We argue the significant potential for synergistic codesign of cryptography and hardware, where customized hardware accelerates cryptographic protocols that are designed with hardware acceleration in mind. As a concrete example, we present a new design of a zero-knowledge proof (ZKP) accelerator that leverages hardware-algorithm co-design to generate proofs 500 times faster than a 32-core CPU.
Bio:
Srini Devadas is the Edwin Sibley Webster Professor of EECS at the Massachusetts Institute of Technology, where he has been on the faculty since 1988. Devadas has worked in the fields of Computer-Aided Design, computer architecture, computer security, and applied cryptography. His work in these fields has resulted in seven "test-of-time" awards, given to papers at least ten years after publication, and resulted in deployments in commercial secure hardware circuits and processors, and popular messaging applications. Devadas is a MacVicar Faculty Fellow and an Everett Moore Baker teaching award recipient, considered MIT's two highest undergraduate teaching honors.