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Advanced Packaging Architectures for Heterogeneous Integration

Event Type
Seminar/Symposium
Sponsor
Department of Mechanical Science and Engineering
Location
190 Engineering Sciences Building
Date
Dec 10, 2019   3:00 pm  
Speaker
Dr. Ravi Mahajan, Intel Director and the Director of Pathfinding for Assembly and Packaging technologies for future silicon nodes, Intel
Contact
Lindsey Henson
E-Mail
lrh@illinois.edu
Phone
217-300-8238
Views
421
Originating Calendar
MechSE Seminars

Abstract:

In recent years advanced packaging technologies have gained considerable attention because of their importance as compact, power efficient platforms for heterogeneous integration (HI).  This talk will trace the evolving role of packaging over the past decades and examine its value as an HI platform.  Different packaging architectures will be compared primarily on the basis of their physical interconnect capabilities.  Key features in leading edge 2D and 3D technologies, such as EMIB, Silicon Interposer, Foveros and Co-EMIB will be described and a roadmap for their evolution will be presented.  The talk will conclude with a discussion of research and advanced development opportunities and challenges in driving the package roadmap forward.

Bio:

Ravi Mahajan is an Intel Fellow and the Director of Pathfinding for Assembly and Packaging technologies for future silicon nodes. Ravi also represents Intel in academia through research advisory boards, conference leadership and participation in various student initiatives. Ravi has led efforts to define technology envelopes for package architecture, technologies and assembly processes at Intel since 2000, spanning 90nm, 65nm, 45nm, 32nm, 22nm and 7nm silicon. Earlier in his Intel career, he spent five years as group manager for thermal mechanical tools and analysis, where he oversaw a Thermal-Mechanical Lab chartered with delivering detailed thermal and mechanical characterization of Intel’s packaging solutions for current and future processors.  A prolific inventor and recognized expert in microelectronics packaging technologies, Ravi holds more than 40 patents, including the original patent for a silicon bridge that became the foundation for Intel’s EMIB technology. His early insights also led to high-performance, cost-effective cooling solutions for high-end microprocessors and the proliferation of photo-mechanics techniques used for thermo-mechanical stress model validation. Ravi has written several book chapters and papers on topics related to his area of expertise.  Ravi joined Intel in 1992 after earning a bachelor’s degree from Bombay University, a master’s degree from the University of Houston, and a Ph.D. from Lehigh University, all in mechanical engineering. His contributions during his Intel career have earned him numerous industry honors, including the SRC’s 2015 Mahboob Khan Outstanding Industry Liaison Award, the 2016 THERMI Award from SEMITHERM, the 2016 Allan Kraus Thermal Management Medal & the 2018 InterPACK Achievement award from ASME and IEEE 2019 “Outstanding Service and Leadership to the IEEE” Award for both the Phoenix Section & IEEE Region 6. He is an IEEE EPS Distinguished Lecturer.  He is one of the founding editors for the Intel Assembly and Test Technology Journal (IATTJ) and currently VP of Publications & Managing Editor-in-Chief of the IEEE Transactions of the CPMT.  Additionally he has been long associated with ASME’s InterPACK conference and was Conference Co-Chair of the 2017 Conference.  Ravi is a Fellow of two leading societies, ASME and IEEE.  He was named an Intel Fellow in 2017.

Host:  Professor Sanjiv Sinha 

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