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Seminar: Boosting Design Productivity for the Internet of Billons of Things

Event Type
Advanced Digital Sciences Center
ADSC Boardroom - Singapore
Dec 22, 2014   11:00 am  
Illinois Associate Professor Deming Chen

Abstract: The Internet has become the most pervasive technology, which has infiltrated every aspect of our lives. It is predicted that there will be 50 billion devices connected through the Internet by 2020. This explosion of devices naturally demands low design cost and fast time-to-market for producing highly energy-efficient ICs. Meanwhile, big data accumulated through these devices need to be processed timely, which demands high processing power under energy constraints for datacenters.  Such substantial demands on high performance and energy efficiency would lead to continued increases of IC complexity and capacity. However, a significant problem is that the design productivity for complex ICs has been lagging behind. High-level synthesis (HLS) has been touted as a solution to this problem, as it can significantly reduce the number of man hours required for a design by raising the level of design abstraction. However, existing HLS solutions have several limitations, and studies show that the design quality of HLS can be noticeably worse than that of manual RTL design. In this talk, I will present several new techniques we developed to drastically improve HLS solutions. These include design entry with parallel languages, smart design space exploration, logic/high-level co-optimization, automatic iterative improvement, and communication optimization across multiple modules, etc. As one example, our code transformation and optimization using polyhedral model can enable data streaming across two communicating hardware modules through HLS, which achieved 30X execution speedup over the baseline on average.

 Bio: Deming Chen is an Associate Professor of Electrical and Computer Engineering of University of Illinois at Urbana-Champaign and a seconded faculty member in the ADSC center. He received his Ph.D. in Computer Science from University of California at Los Angeles in 2005. His research interests include system- and high-level synthesis, compilation and programming for heterogeneous platforms, nano-systems design, GPU optimization, and bioinformatics. He is a technical committee member for a series of conferences, including FPGA, ASPDAC, ICCD, ISQED, DAC, ICCAD, DATE, ISLPED, FPL, etc. He is or has been an associated editor for TCAD, TVLSI, TODAES, TCAS-I, JCSC, and JOLPE. He is the program chair and general chair for several conferences. He received five Best Paper Awards, the NSF CAREER Award in 2008, the ACM SIGDA Outstanding New Faculty Award in 2010, and IBM Faculty Award in 2014. He is a senior member of IEEE. He was involved in two startup companies. He implemented his published algorithm on CPLD technology mapping when he was a software engineer in Aplus Design Technologies, Inc. in 2001, and the software was exclusively licensed by Altera. He is one of the inventors of the xPilot high-level synthesis package developed at UCLA, which was licensed to AutoESL Design Technologies, Inc.

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