Joint Computer Science and Electrical and Computer Engineering Seminar
Dr. Scott Beamer
Assistant Professor, University of California, Santa Cruz
Tuesday, June 25, 2024, 10:00-11:00 am
Online via Zoom
Title: Graphs: From Social Networks to Hardware Simulation
Abstract: In the twilight of Moore’s Law, computing applications can no longer depend on improvements in chip manufacturing and general-purpose processor architecture to significantly improve performance. Vertically optimizing across hardware-software boundaries to utilize both software optimization and hardware specialization to achieve efficiency improvements is essential to enable future applications.
In this talk, I will introduce the work of my research program, the Vertical Architectures, Memories, and Algorithms (VAMA) group. We utilize a vertically-integrated approach to deliver substantial computing efficiency gains for data-intensive applications including graph processing, hardware simulation, zero-knowledge proofs, and pangenomics. Our novel approach is built on a foundation in computer architecture, which we complement with application domain expertise and empirical data-driven analysis.
Graphs, are a flexible abstraction used throughout computing, and they are a common theme to much of our work. We will survey the insights from our workload characterization and benchmarking that enabled our algorithmic innovations (breadth-first search and propagation blocking). We will also preview our ongoing collaboration to codesign a supercomputer for massive-scale graph processing. We will go in depth on how our expertise on graphs and processor micro-architecture enabled us to create the fastest software RTL simulators, for both single-thread (ESSENT) and multicore (RepCut). We will conclude by discussing our plans for future work.
Scott Beamer is an assistant professor of Computer Science & Engineering at the University of California, Santa Cruz where he leads the Vertical Architectures, Memory, and Algorithms (VAMA) research group. His research interests include agile hardware design, high-performance graph processing, and computer architecture. His work has been recognized with an NSF CAREER Award, the Kaivalya Dixit Distinguished Dissertation Award from SPEC, best paper awards from the International Parallel & Distributed Processing Symposium (IPDPS) and the International Symposium on Workload Characterization (IISWC), and a distinguished paper award from International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS). He earned his PhD in Computer Science from UC Berkeley where he was advised by Krste Asanović and David Patterson, and he was an early contributor to RISC-V. Prior to becoming faculty, he was a postdoctoral scholar at Lawrence Berkeley National Laboratory.
