A brief overview of present understanding of tradeoff between Energy and Errors in Computing will be presented. There is a large body of research that claims that a tradeoff exists between energy and accuracy of computing. The basis of such claims come from the understanding of a chip’s behavior under large Process Variations with statistical delay assumptions. It leads one to conclude that a small number of errors are likely as we lower the supply voltage to save energy. This understanding is challenged by the speaker with his new hypothesis on the behavior of large CMOS chips in the presence of process variations. A Thought Experiment is presented which leads to the new hypothesis. The new hypothesis states that in every large CMOS chip, there exist Critical Operations Points (Frequency, Voltage) such that it divides the 2-D space (F, V) in to two distinct spaces: 1. Error-free operation and 2. Massive number of Errors (i.e., completely inoperable). Two attempts at disproving this hypothesis with real physical experiments will be described. The conclusion reached is that Energy-Accuracy tradeoff is not possible in microprocessor sized chips. But the good news is that we can save energy by lowering Voltage down to Critical Voltage and not worry about an error occurring.
