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AVS Student Chapter presents Angel Yanguas-Gil (Argonne National Laboratory): "In-situ characterization, theory, and co-design approaches to accelerate the development of novel thin film processes and devices."

Event Type
MRL 280
Feb 20, 2020   1:00 pm  
Originating Calendar
Illinois ECE Calendar


In this talk I will focus on how the combination of in-situ techniques, simulation and theory, and co-design approaches can help accelerate the development and transition to manufacturing of new processes in the fields of atomic layer deposition (ALD) and on-chip learning for edge processing applications.

While ALD is an enabling technique for semiconductor processing applications and it is emerging as a manufacturing tool for energy technologies, only a fraction of the 1000s of processes reported in the literature behaves as it is traditionally expected from an ideal ALD process. In this talk I will introduce general models that predict the performance of ALD process for different manufacturing approaches, and how the exploration of the fundamentals of precursor-surface, ligand-surface, and precursor-ligand interactions using in-situ QCM, FTIR, and synchrotron techniques can help us understand the mechanistic aspects behind some of the non-ideal behaviors observed and their impact during scale up to high surface area materials and large area substrates. Through the integration of machine learning with in-situ techniques and simulations we have also demonstrated the ability to carry out real time process optimization.

In the second part of my presentation, I will focus on how we can further use co-design approaches to accelerate the integration of emergent materials in microelectronics applications: in the context of onchip learning, we are tracing back the steps from novel algorithms to FPGA design, neuromorphic chips such as Intel’s Loihi, and finally to the emulation of architectures integrating novel devices to identify design targets for emergent materials. These lead to similar performances with a much lower power consumption, and the resulting architectures are robust to process variability and write errors exceeding 20%. We are currently generalizing this approach through the integration of functional emulation and SPICE-level simulation with machine learning frameworks to achieve a massively parallel exploration and optimization of novel architectures.

Refreshments will be provided.

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